1. Field of the Invention
The invention relates to multiplexers of digital signals. More particularly, the invention concerns a digital multiplexer with a short data to output propagation delay and low power consumption.
2. Description of the Related Art
Multiplexers, which are common components of digital logic systems, allow one of a number of inputs to be connected to an output. It is desirable to transmit data from an input of a multiplexer to the output of the multiplexer with as little delay as possible, and with as little power dissipation as possible.
A conventional implementation of a 16:1 multiplexer is to cascade a number of 2:1 multiplexers, as shown in FIG. 1. Alternatively, other sized multiplexers, for example 4:1 multiplexers, can be cascaded in a similar fashion. In the multiplexer in FIG. 1, D1, D2, . . . D16 are the data inputs, Y is the output, and S0, S1, S2, and S3 are the select lines. Because each 2:1 multiplexer adds one gate delay, this circuit requires four gate delays to transmit data from an input to the output. Also, because each 2:1 multiplexer requires a current source, this circuit requires fifteen current sources.
In order to reduce power consumption, and also to reduce the data to output propagation delay, which is the time from when a data input changes state to the time that the output changes state, it is known in the art to construct a multiplexer that does not require a cascade of smaller multiplexers, and in which a single current source is used for all of the inputs. However, the data to output propagation delay for these multiplexers is still too long for many applications. The data to output propagation delay in these multiplexers is too long primarily due to the relatively large amount of capacitance associated with the collector(s) of the input transistors, which is connected to the base of the output transistor.
Consequently, there is a need for a multiplexer with low power consumption and with a reduced data to output propagation delay.